Overview In pipelined processors, an instruction must be fetched at every clock cycle in order to sustain the pipeline. However, in modern processors, the decision of whether or not to take a branch is not made until the memory-access stage of the pipeline, and the pipeline must stall the fetching of the next instruction until the decision is made. Because on average 20% of instructions are fetches, this causes a significant penalty on the performance of …showed first 75 words of 1041 total…

…showed last 75 words of 1041 total…the information has to be collected again, so there is another warm-up phase every time there is a context switch. In addition, aliasing becomes more of an issue in two-level predictors. Aliasing is when different branch addresses are mapped to the same table entry. Aliasing occurs when the table size is limited, and there are more branch instructions than table entries. Aliasing is not always harmful, however. Sometimes it even leads to more accurate predictions.